Semiconductor wafer processing apparatus and method

ABSTRACT

A wafer stage  2  for holding a semiconductor wafer in a plasma treatment apparatus by setting the wafer on the wafer stage, said wafer stage  2  comprising a base material  26  equipped with refrigerant flow paths for allowing a refrigerant for temperature adjustment to flow; a stress-reducing member  28  provided on the wafer setting side of said base material  26  and having a smaller thermal expansion coefficient than does said base material; a dielectric film  30  provided on the wafer setting side of said stress-reducing member; and a deflection-preventing member  29  provided on the wafer non-setting side of said base material and having a smaller thermal expansion coefficient than does said base material. When the wafer stage is used, the temperature of the wafer as a substrate to be processed can be controlled uniformly and very accurately.

BACKGROUND OF THE INVENTION

[0001] This invention relates to a wafer stage and a processingapparatus and a processing method which use the wafer stage. Inparticular, it relates to, for example, the wafer stage which permitsuniform and very accurate control of the temperature of a wafer as asubstrate to be processed.

[0002] In recent years, circuit patterns have become finer steadily withan enhancement of the degree of integration of semiconductor devices, sothat the dimensional accuracy in fabrication has required to becomehigher and higher. In such a situation, it is very important to controlthe temperature of a wafer under processing.

[0003] For example, in an etching process that is required to give ahigh aspect ratio, etching is conducted while protecting the sidewallwith an organic polymer in order to realize anisotropic etching. In theprocess, the production of the organic polymer as a protective filmchanges with temperature. Therefore, if the temperature distribution ofa wafer under processing is not uniform, the thickness of the sidewallprotective film produced is not uniform depending on a position on thewafer surface, so that the shape of etched portion is not uniform.

[0004] In recent semiconductor production processes, the diameter of awafer is increased in order to reduce the production cost, and the heatinput to the wafer tends to be increased more and more. Therefore-,controlling the temperature of the wafer surface uniformly is a veryimportant technical problem. For example, in a process of etching aninterlaminar insulating film in a processing line in which the diameterof a wafer is 300 mm, a bias electric power applied to the wafer reachesabout 3 kW and the wafer is heated by this electric power.

[0005] The wafer under plasma treatment in the above-mentionedproduction process is electrostatically attracted and held on a stage bymeans of an electrostatic chuck. The aforesaid wafer is cooled byintroducing a thermally conductive gas (usually, helium) into the spacebetween the wafer and the stage.

[0006] The structure of the electrostatic chuck is varied depending onthe specifications of each apparatus. In general, the structure is suchthat a ceramic film of about 1 mm or less in thickness is attached tothe surface of a metal good in thermal conduction used as a base, suchas aluminum. Refrigerant flow paths are provided in the base metal, andthe electrostatic chuck is cooled by allowing a refrigerant whosetemperature is controlled by means of a thermoregulator provided outsidethe apparatus, to flow along the aforesaid flow paths.

[0007] The permissible temperature range of a wafer to be controlledvaries depending on a process. For example, the temperature of a stagefor holding the wafer is required to be stable in a wide temperaturerange from a low temperature of about −40° C. to a high temperature ofabout 100° C. That is, the wafer stage of a plasma treatment apparatusis required to realize a uniform temperature distribution in a widetemperature range on the whole surface of a wafer having a largediameter, even at a high heat input.

[0008] However, in a stage having such a structure as is describedabove, the thermal expansion coefficients of the base metal and thedielectric film are widely different. Therefore, no problem is causedwhen the working temperature is approximately 20° C. to 40° C. However,in a temperature range of 80° C. to 100° C., a high thermal stress isgenerated in the dielectric film owing to the difference between thethermal expansion coefficients of the base metal and the dielectricfilm, so that the film is broken in some cases. In this case, the stageshould be replaced after stopping an apparatus.

[0009] JP-A-11-176919 discloses a wafer stage capable of solving theabove problem. In the apparatus disclosed therein, a ceramic sinteredproduct is attached to a composite material of aluminum and a ceramic bybrazing; an electroconductive brazing material or a metal with a thermalexpansion coefficient close to that of a dielectric film, such astitanium or molybdenum is embedded as the electrode of an electrostaticchuck in the ceramic sintered product; and a dielectric layer is formedon the surface of the ceramic sintered product.

[0010]FIG. 12 is a diagram showing a plasma treatment apparatus usinganother conventional wafer stage, and FIG. 13 is an enlarged view of thewafer stage shown in FIG. 12.

[0011] First, an etching gas 11 is introduced into a vacuum chamber 9,and the pressure inside the vacuum chamber 9 is maintained at a suitablepressure by adjusting the opening of a valve 12 provided upstream to aturbo-molecular pump 13. A parallel-plate upper electrode 10 is locatedover a wafer stage 2 in the vacuum chamber 9. Plasma 6 is generated inthe vacuum chamber by applying a high-frequency voltage of 13.56 MHz tothe upper electrode 10 by using a high-frequency power source 8.

[0012] Etching can be conducted by exposing a wafer 1 to the plasma. Thewafer is set on the wafer stage 2 located so as to face the upperelectrode. The wafer stage 2 is fixed on an insulating member 7 fixed ona flange 5, by means of bolts 19, and is electrically insulated from thevacuum chamber 9. The wafer stage 2 is such that a 1-mm thick dielectricfilm 21 composed mainly of a ceramic is attached to the surface of abase material 17 made of aluminum, by flame spraying or the like.

[0013] A through-hole 14 for introducing helium gas is provided in thecenter of the wafer stage. The flow rate of the gas introduced can beadjusted by controlling a flow rate regulator 25 on the basis of a valuemeasured with a pressure gage 24 attached to a gas piping 23 under thereverse side of the wafer.

[0014] In the peripheral portion of the wafer stage, twelve bolt holesfor fixing on the insulating member are provided in the peripheraldirection. On the reverse side of the base material, refrigerant grooves15 are provided in concentric circles. The above-mentioned flange 5 isfixed on the vacuum chamber 9 by means of bolts 4. An O-ring 3 preventsa refrigerant for cooling the wafer stage from leaking into thetreatment chamber.

[0015] The wafer stage 2 is connected to an external high-frequencypower source 20 while being electrically insulated from the flange by aninsulating material 18. For example, a high-frequency bias voltage of800 kHz is applied to the wafer stage 2. Thus, a bias voltage isgenerated in the wafer, so that ions can be effectively introduced intothe wafer. Accordingly, the etching capability can be improved: forexample, anisotropic etching can be realized, and the etching rate canbe increased.

[0016] However, in the method described above, the ions heat the wafersimultaneously with their introduction into the wafer. Therefore, thewafer should be externally cooled. The wafer stage 2 can be cooled bycirculating a refrigerant controlled at a definite temperature, from arefrigerator provided outside the vacuum chamber 9, to the refrigerantgrooves 15 provided in the base material 17. However, under usualetching conditions, the pressure inside the treatment chamber is somepascals. Since the pressure is low, the thermal resistance between thewafer and the wafer stage is high, so that the wafer cannot besufficiently cooled. Therefore, the cooling efficiency is usuallyimproved by introducing an inert and thermally conductive gas such ashelium gas into the space between the wafer and the wafer stage.Usually, the pressure of the gas is approximately 500 Pa to 2 kPa. Inorder to prevent the wafer from moving to a position different from thatof the wafer stage owing to the gas pressure, the wafer iselectrostatically attracted on the wafer stage by applying adirect-current voltage to the wafer stage from a direct-current powersource 22. The wafer is substantially at earth potential because it isin contact with the plasma. Therefore, a potential difference is made inthe dielectric film 21 between the wafer and the wafer stage owing tothe direct-current power source 22, and the wafer is electrostaticallyattracted by Coulomb's force of electric charges due to said potentialdifference.

SUMMARY OF THE INVENTION

[0017] In the apparatus according to the above reference JP-A-11-176919,the composite material of aluminum and a ceramic is used as a basematerial because a sintered ceramic for reducing a stress between thedielectric layer and the base material is provided on the base materialas described above. Such a composite material, however, usually costsmore than aluminum. In addition, since the aforesaid ceramic used as astress-reducing layer is an insulating material, an electric connectorshould be provided between the electrode layer and the base material,resulting in a complicated structure. Moreover, the aforesaid ceramicbecomes a thermal resistance, so that the controllability of thetemperature of a wafer is deteriorated.

[0018]FIG. 14 and FIG. 15 are graphs showing the temperaturedistribution on the surface of a wafer (diameter: 8 inches) and thestress distribution on the surface of the dielectric film, respectively,in the above-mentioned conventional plasma treatment apparatus (heatinput: 200 W).

[0019] A bias electric power of 200 W is input to the wafer stage, andthe temperature of the refrigerant circulated in the wafer stage iscontrolled at 20° C. In this case, the temperature difference on thewafer surface was about 9° C., and the maximum principal stressgenerated in the dielectric film was about 6 kgf/mm² or less. The causeof the stress generation in the dielectric film is the differencebetween the thermal expansion coefficients of aluminum as the basematerial and the ceramic as the dielectric film. In calculating thestress, it was assumed that the thermal expansion coefficient ofaluminum is 23×10⁻⁶ (1/K) and that of the ceramic 10×10⁻⁶ (1/K). Whenthe temperature difference on the wafer surface and the stress arevalues shown in the figures, the treatment can be carried out withoutdeterioration of etching characteristics and breakage of the dielectricfilm.

[0020] In recent years, increasing the bias electric power to about 1 kWhas come to be required for further increasing the etching rate. Inaddition, the temperature of the wafer stage is required to be adjustedto a high temperature of approximately 80° C. to 100° C. or a lowtemperature of approximately −40° C. to 0° C. in some cases, dependingon a process. When the treatment is carried out under such conditions,the temperature distribution on the wafer surface is deteriorated andmoreover, a high stress is generated in the dielectric film, so that thedielectric film is liable to be broken.

[0021]FIG. 16 and FIG. 17 are graphs showing the temperaturedistribution on the surface of a wafer (diameter: 8 inches) and thestress distribution on the surface of the dielectric film, respectively,in the above-mentioned conventional plasma treatment apparatus (heatinput: 1 KW).

[0022] A bias electric power of 1 KW is input to the wafer stage, andthe temperature of the refrigerant circulated in the wafer stage iscontrolled at 20° C. In this case, the temperature of the wafer in thevicinity of its periphery is higher than that in the vicinity of thecenter, and there is a temperature difference of about 46° C. on thewafer surface. In such a situation, etching characteristics are notuniform because those in the center of the wafer are different fromthose in the vicinity of the periphery. Consequently, the productperformance characteristics finally attained are not uniform and theyield is decreased. In order to prevent the rise of temperature of thewafer in the vicinity of its periphery, providing of refrigerant groovesalso in the vicinity of the periphery is thought of. However, in thecase shown in FIGS. 16 and 17, the O-ring 3 for preventing the leakageof the refrigerant is necessary in the peripheral portion, so that it issubstantially impossible to provide refrigerant grooves in theperipheral portion.

[0023]FIG. 17 shows the distribution of maximum principal stress on thesurface of the dielectric film which was calculated by raising therefrigerant temperature in 20° C. steps from 0° C. to 80° C. As shown inFIG. 17, the maximum principal stress increase with a rise of therefrigerant temperature and exceeds 20 kgf/mm² at 80° C.

[0024] According to our experiences, the dielectric film tends to becracked at a stress of more than 20 kgf/mm² though the cracking dependson a method for attaching the dielectric film to the wafer stage. If thedielectric film is cracked, the attraction of the wafer becomesimpossible.

[0025] The present invention was made in view of problems describedabove and provides a wafer stage which permits uniform and very accuratecontrol of the temperature of a wafer as a substrate to be processed.

[0026] In order to solve the above problems, the following means wasemployed in the present invention.

[0027] A wafer stage for holding a semiconductor wafer in a plasmatreatment apparatus by setting the wafer on the wafer stage, said waferstage comprising a base material equipped with refrigerant flow pathsfor allowing a refrigerant for temperature adjustment to flow; astress-reducing member provided on the wafer setting side of said basematerial and having a smaller thermal expansion coefficient than doessaid base material; a dielectric film provided on the wafer setting sideof said stress-reducing member; and a deflection-preventing memberprovided on the wafer non-setting side of said base material and havinga smaller thermal expansion coefficient than does said base material.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 is a diagram showing a wafer processing apparatus equippedwith a wafer stage according to a first embodiment of the presentinvention.

[0029]FIG. 2 is an enlarged view of the wafer stage.

[0030]FIG. 3 is a graph showing the stress distribution of thedielectric film of the wafer stage.

[0031]FIG. 4 is a diagram showing a semiconductor device which permitsprocessing using a plasma treatment apparatus.

[0032]FIG. 5 is a chart illustrating effects obtained by the use of aplasma treatment apparatus according to the first embodiment.

[0033]FIG. 6 is a chart illustrating the effects obtained by the use ofthe plasma treatment apparatus according to the first embodiment.

[0034]FIG. 7 is a chart showing a second embodiment.

[0035]FIG. 8 is a diagram showing a third embodiment.

[0036]FIG. 9 is a diagram showing the third embodiment.

[0037]FIG. 10 is a diagram showing a fourth embodiment.

[0038]FIG. 11 is a diagram showing the fourth embodiment.

[0039]FIG. 12 is a diagram showing a plasma treatment apparatus using aconventional wafer stage.

[0040]FIG. 13 is an enlarged view of the wafer stage portion.

[0041]FIG. 14 is a graph showing the temperature distribution on thesurface of a wafer in a conventional plasma treatment apparatus.

[0042]FIG. 15 is a graph showing the stress distribution on the surfaceof the dielectric film in the conventional plasma treatment apparatus.

[0043]FIG. 16 is a graph showing the temperature distribution on thesurface of a wafer in the conventional plasma treatment apparatus.

[0044]FIG. 17 is a graph showing the stress distribution on the surfaceof the dielectric film in the conventional plasma treatment apparatus.

DETAILED DESCRIPTION OF THE INVENTION

[0045] The embodiments of the present invention are explained below withreference to the attached drawings. FIG. 1 is a diagram showing a plasmatreatment apparatus equipped with a wafer stage according to a firstembodiment of the present invention. FIG. 2 is an enlarged view of thewafer stage portion. In these figures, explanation of the same parts asshown in FIG. 12 and FIG. 13 is omitted by expressing these parts by thesame symbols, respectively, as in FIG. 12 and FIG. 13. In the presentembodiment, an aluminum plate 27 is brazed to the under surface of abase material 26 having refrigerant grooves formed therein. When such astructure is employed, an O-ring for preventing the leakage of arefrigerant is unnecessary, so that the refrigerant grooves can be alsoin the closer vicinity of the periphery. Therefore, the temperaturedistribution on the surface of a wafer can be made more uniform bykeeping the temperature of the wafer in the vicinity of its peripherylow.

[0046] A stress-reducing member 28 made of titanium is brazed to the topsurface of the base material, and a ceramic dielectric film 30 of 1 mmin thickness is attached to the stress-reducing member by flamespraying. Thus, it becomes possible to prevent the generation of a highstress which is caused in the dielectric film when a high-temperaturerefrigerant is allowed to flow.

[0047] A deflection-preventing member 29 made of titanium is also brazedto the under surface of the base material through the aluminum plate 27.Thus, it becomes possible to prevent warping caused by the difference instiffness between the base material and the stress-relaxing member.

[0048] In the present embodiment, the stress-reducing member to whichthe dielectric film is attached has a thermal expansion coefficient of8.6×10⁻⁶ (1/K) which is smaller than that of the aluminum base materialand is close to that of the dielectric film 10×10⁻⁶ (1/K). Therefore, afilm stress generated in the dielectric film can be reduced, so that thewafer stage can be used even in a process practiced at a highertemperature.

[0049]FIG. 3 is a graph showing the stress distribution of thedielectric film of the wafer stage in the present embodiment. As shownin FIG. 3, a stress generated in the dielectric film is reduced to about5 kgf/mm² from a conventional value of more than 20 kgf/mm². At thereduced stress value, the film is not cracked. That is, the aforesaidwafer stage can be used in either a high-pressure or low-pressureprocess.

[0050] Although the ceramic film as the dielectric film is attached tothe stress-reducing member by flame spraying, a ceramic sintered productmay be attached by brazing or with an adhesive. Although the thicknessof the dielectric film is 1 mm in the above case, it should be properlydetermined depending on the pressure of helium and the film propertiesof the dielectric used. In the present embodiment, a material for thebase material having the refrigerant flow paths formed therein isaluminum and a material for the stress-reducing member and thedeflection-preventing member is titanium, though a combination of thesematerials is not limited to the above combination. That is, thefollowing are necessary conditions: the thermal conductivity of the basematerial having the refrigerant grooves formed therein is larger thanthat of the stress-reducing member and that of the deflection-preventingmember, and the thermal expansion coefficient of the stress-reducingmember is close to that of the dielectric film. When these conditionsare satisfied, a temperature gradient is hardly given to the basematerial, so that the uniform temperature distribution of a wafer can berealized. Moreover, a film stress generated in the dielectric film isreduced, resulting in an improved reliability.

[0051]FIG. 4 is a diagram showing a semiconductor device which permitsprocessing using a plasma treatment apparatus. As shown in FIG. 4, gateelectrodes 44, a tungsten (W) wiring 45 and interlaminar insulatingfilms 41 and 42 are formed on a silicon substrate 40. A resist mask 43is formed on said interlaminar insulating film 42, and perforation forcontact with the tungsten (W) wiring 45 is carried out by utilizing themask. The thickness of the interlaminar insulating film 42 is 2 μm, thediameter of each hole formed in said film is 0.3 μm, and the perforationis carried out by etching using a fluorine-containing gas.

[0052]FIG. 5 and FIG. 6 are diagrams illustrating effects obtained bythe use of the plasma treatment apparatus according to the presentembodiment. FIG. 5 is a time chart of treatment in a conventionaltreatment apparatus, and FIG. 6 is a time chart of treatment in thetreatment apparatus according to the present embodiment.

[0053] In FIG. 5, a wafer is set at first on the wafer stage by the useof a conveying system equipped with the treatment apparatus (101). Next,a treatment chamber is evacuated for 5 seconds and then the pressureinside the treatment chamber is controlled at a definite pressure byintroducing a treating gas thereinto (102). After the pressure insidethe treatment chamber reached a set value about 3 seconds after thestart of the gas introduction, plasma discharge is initiated (103).After 0.5 second, a direct-current voltage for an electrostatic chuck isapplied to attract the wafer (104). After another 1 second, helium gasis allowed to get under the reverse side of the wafer and its flow rateis controlled with a flow rate controller so that the pressure of heliummay become a set value (105). After about 1 second, the pressure ofhelium reached the set value, and then a bias electric power is input tothe wafer stage (106).

[0054] In this case, the temperature of the wafer stage is 0° C. and thebias electric power is 1 kW. Since the etching rate attained under theseconditions is 400 nm/min, the treatment time (the etching time) is 5minutes. After completion of the etching, the application of the biaselectric power is stopped (107). After 0.5 second, the helium gas isexhausted (108). After another 0.5 second, the exhaustion of the heliumgas is completed, and hence the voltage application to the electrostaticchuck is stopped (109). The electric charge generated in the wafer isreleased into the plasma by exposing the wafer to the plasma for 2seconds.

[0055] Since the attracting force for the wafer is lost owing to theabove operations, the wafer becomes conveyable and the plasma dischargeis stopped (110). After 0.5 second, the introduction of the treating gasis stopped and the treatment chamber is evacuated (111). After 2seconds, the pressure inside the treatment chamber reached a definitepressure or lower, and then carrying-out of the treated wafer andcarrying-in of a wafer to be treated are initiated (112). Numeral 113indicates a point of time at which the carrying-out of the new wafer hasbeen completed, and the total time required for the carrying-in and thecarrying-out is 30 seconds. In the above example of the treatment, atime required per wafer is a period from numeral 101 to numeral 113 andis 5 minutes 46 seconds in total.

[0056]FIG. 6 is a time chart of treatment in the plasma treatmentapparatus according to the present embodiment as described above. In thecase of the wafer stage according to the present embodiment, thetemperature distribution of a wafer set on the wafer stage can beimproved and moreover, a stress generated in the dielectric film on thewafer stage can be reduced. Therefore, a bias electric power input tothe wafer stage can be increased to 2 kW from a conventional input of 1kW. Consequently, the etching rate can be increased to 600 nm/min from aconventional rate of 400 nm/min. That is, a period of the application ofthe bias electric power (a period from numeral 106 to numeral 114) canbe reduced to 3 minutes 20 seconds from a conventional period of 5minutes. A time required for the operations other than the applicationof the bias electric power is the same as that conventionally required.Therefore, in the case shown in FIG. 6, a time required per wafer isreduced to 4 minutes and 6 seconds from a conventional time of 5 minutesand 46 seconds. That is, in the treatment apparatus according to thepresent embodiment, the wafer temperature distribution can be keptuniform and the generation of a stress in the dielectric film can besuppressed, even at a high heat input. Therefore, the throughputcapacity of the apparatus can be greatly improved.

[0057]FIG. 7 is a chart showing a second embodiment of the presentinvention. In this embodiment, the temperature of a wafer is directlymeasured from the reverse side of the wafer, and etching is controlledon the basis of the temperature information obtained. The temperature ofthe wafer may be measured with, for example, a fluoro-thermometer or athermocouple. By such a means, the temperature of the wafer is measuredat first (121). Then, the measurement data are sent to an externalcomputer connected, to be subjected to arithmetic processing, wherebythe temperature of the wafer is calculated (122). The temperature dataobtained are compared with a previously set temperature range (123).When it was found as a result of the comparison that the temperature ofthe wafer is in a normal range, the treatment is continued (125). If thetemperature of the wafer is not in the normal range, the treatment isstopped and the detection of an abnormality is indicated in a placeconvenient for recognition by an operator, such as the display of thecomputer (124).

[0058] In the above treatment method, since quick measures can beadopted when an abnormality occurs in the treatment, the production of alarge number of defective wafers is prevented, namely, the manufacturingcost can be kept low.

[0059] Although the temperature of the wafer is directly measured in thepresent embodiment, the direct measurement of the wafer temperature isnot always necessary. The temperature of the wafer under treatment canbe predicted, for example, by monitoring the temperature at any positionof the wafer stage, for instance, the temperature of the refrigerant,and using the previously determined relationship between the refrigeranttemperature and the wafer temperature.

[0060]FIG. 8 and FIG. 9 are diagrams showing a third embodiment of thepresent invention. FIG. 8 is a diagram showing a wafer processingapparatus equipped with a wafer stage, and FIG. 9 is an enlarged view ofthe wafer stage portion. In FIG. 9, numeral 31 denotes a staircase-likelevel difference portion formed in a stress-reducing member. Said leveldifference portion has a diameter smaller than the outside diameter of asemiconductor wafer to be set thereon. In FIG. 8 and FIG. 9, explanationof the same parts as shown in FIG. 12 and FIG. 13 is omitted byexpressing these parts by the same symbols, respectively, as in FIG. 12and FIG. 13. When the wafer stage is used in the processing apparatus, asilicon ring 32 (called, for example, a focus ring) is mounted on adielectric film around the periphery of the level difference portion. Insuch a situation, plasma is produced in a processing chamber in the samemanner as in the case shown in FIG. 1, and a direct-current voltage isapplied to the wafer stage, whereby the ring is electrostaticallyattracted like the wafer. When a bias electric power is input to thewafer stage thus treated, a bias potential is generated also in thering, so that accelerated ions penetrate also into the ring from theaforesaid plasma.

[0061] According to the present embodiment, the excess fluorine radicalsin the plasma can be removed by the use of the aforesaid ring to realizea plasma distribution which is uniform from the center of the wafer toits periphery. Therefore, etching characteristics on the wafer surfacecan be made uniform. That is, the present embodiment is advantageouswhen an insulating film is etched with a fluorine-containing plasma.

[0062] Furthermore, according to the present embodiment, more uniformetching characteristics can be attained because the focus ring can becooled while assuring the uniformity of the wafer temperature. As amaterial for the aforesaid ring 32, carbon, SiC and the like can beutilized besides silicon.

[0063]FIG. 10 and FIG. 11 are diagrams showing a fourth embodiment ofthe present invention. FIG. 10 is a diagram showing a wafer processingapparatus equipped with a wafer stage. FIG. 11 is an enlarged view ofthe wafer stage portion. As shown in FIG. 10 and FIG. 11, a leveldifference portion 38 is formed in the peripheral portion of astress-reducing member 35 so that the level difference portion may belower in its peripheral portion than in the vicinity of the center. Aninsulating layer (for example, a dielectric film 33) for electricalinsulation from the stress-relaxing member is formed at the periphery ofthe aforesaid level difference portion 38. Ring-shaped tungsten internalelectrodes 34 are formed on the insulating layer. In addition, adielectric film 33 for attracting a wafer is further attached onto theinsulating layer by flame spraying. The internal electrodes 34 areconnected to an external direct-current power source 37 through aninsulating material 36. The polarity of the direct-current power source37 is reverse to that of the direct-current power source 22. When such astructure is employed, an electric circuit can be formed through thewafer irrespective of the presence of plasma 6, so that the wafer can beattracted. In FIG. 10 and FIG. 11, explanation of the same parts asshown in FIG. 12 and FIG. 13 is omitted by expressing these parts by thesame symbols, respectively, as in FIG. 12 and FIG. 13.

[0064] According to the present embodiment, the attraction of the waferand the introduction of helium gas can be carried out before theinitiation of plasma discharge. Therefore, the control of the wafertemperature can be initiated immediately after the start of processingof the wafer. Moreover, since the wafer can be set or removedirrespective of the presence of plasma, a waiting period for eliminatingthe electric charge of the wafer after completion of the processing isunnecessary, so that the throughput is increased.

[0065] The dielectric film 33 can be formed by not only flame sprayingbut also brazing of a sintered product or attachment of the dielectricfilm with an adhesive. Although the internal electrodes are formed asrings, their shape may be another shape. That is, the wafer can beattracted by supplying different potentials to a plurality of theinternal electrodes, respectively, facing the wafer.

[0066] As described above, according to the present embodiment, therecan be provided a wafer stage on which the temperature distribution of awafer is uniform even at a high heat input. In addition, since a filmstress generated in the dielectric film formed on the surface of thewafer stage can be kept low even at a high temperature, the wafer stagecan be provided as a highly reliable one. When the wafer stage is used,the wafer can be maintained at a uniform temperature without breakage ofthe dielectric film of the wafer stage even at a high heat input to thewafer stage. Therefore, a processing apparatus having a high throughputcapacity can be provided.

[0067] When the temperature of the wafer is abnormal, the processing isimmediately stopped and the abnormality can be reported to an operator.Therefore, wasteful processing of the wafer can be minimized, so thatthe manufacturing cost can be reduced. Furthermore, since the plasma canbe made uniform by virtue of the ring of silicon or the like locatedaround the wafer, etching characteristics on the wafer surface can bekept good.

[0068] As explained above, according to the present invention, there canbe provided a wafer stage which permits uniform and very accuratecontrol of the temperature of a wafer as a substrate to be processed. Byutilizing such a wafer stage, there can be provided a processingapparatus and a processing method, which have a-high throughputcapacity.

What is claimed is:
 1. A wafer stage for holding a semiconductor waferin a plasma treatment apparatus by setting the wafer on the wafer stage,said wafer stage comprising: a base material equipped with refrigerantflow paths for allowing a refrigerant for temperature adjustment toflow, a stress-reducing member provided on the wafer setting side ofsaid base material and having a smaller thermal expansion coefficientthan does said base material, a dielectric film provided on the wafersetting side of said stress-reducing member, and a deflection-preventingmember provided on the wafer non-setting side of said base material andhaving a smaller thermal expansion coefficient than does said basematerial.
 2. The wafer stage according to claim 1, wherein saiddielectric film is a film formed by flame spraying and composed mainlyof a ceramic.
 3. The wafer stage according to claim 1, wherein saiddielectric film is a film formed by chemical vapor deposition andcomposed mainly of a ceramic.
 4. The wafer stage according to claim 1,wherein said dielectric film is a sintered product composed mainly of aceramic.
 5. The wafer stage according to claim 4, wherein the dielectricfilm comprising a sintered product composed mainly of a ceramic isbrazed to said stress-reducing member or attached thereto with anadhesive.
 6. A wafer stage for holding a semiconductor wafer in a plasmatreatment apparatus by setting the wafer on the wafer stage, said waferstage comprising: a base material equipped with refrigerant flow pathsfor allowing a refrigerant for temperature adjustment to flow, astress-reducing member provided on the wafer setting side of said basematerial and having a smaller thermal expansion coefficient than doessaid base material, a dielectric film provided on the wafer setting sideof said stress-reducing member, and a deflection-preventing memberprovided on the wafer non-setting side of said base material and havinga smaller thermal expansion coefficient than does said base material,wherein said stress-reducing member has a cylindrical and internallyconvex level difference portion with a diameter smaller than the outsidediameter of a semiconductor wafer to be set thereon, and a ring membermade of carbon, Si or SiC is mounted on said dielectric film around theperiphery of said level difference portion.
 7. The wafer stage accordingto any one of claims 1 to 6, wherein said dielectric film is equippedwith a plurality of electrodes for electrostatic attraction, anddifferent potentials are supplied to the plurality of the electrodes,respectively.
 8. An apparatus for processing a semiconductor wafer as asubstrate to be processed which comprises a wafer stage comprising: abase material equipped with refrigerant flow paths for allowing arefrigerant for temperature adjustment to flow, a stress-reducing memberprovided on the wafer setting side of said base material and having asmaller thermal expansion coefficient than does said base material, adielectric film provided on the wafer setting side of saidstress-reducing member, and a deflection-preventing member provided onthe wafer non-setting side of said base material and having a smallerthermal expansion coefficient than does said base material, wherein asemiconductor wafer is held in a plasma treatment apparatus by settingthe wafer on said wafer stage, said processing apparatus being equippedwith a control unit for controlling the temperature of the refrigerantto be allowed to flow along the refrigerant flow paths, on the basis ofthe temperature of said substrate to be processed.
 9. A method forprocessing a semiconductor wafer as a substrate to be processed whichuses a wafer stage comprising: a base material equipped with refrigerantflow paths for allowing a refrigerant for temperature adjustment toflow, a stress-reducing member provided on the wafer setting side ofsaid base material and having a smaller thermal expansion coefficientthan does said base material, a dielectric film provided on the wafersetting side of said stress-relaxing member, and a deflection-preventingmember provided on the wafer non-setting side of said base material andhaving a smaller thermal expansion coefficient than does said basematerial; and comprises holding a semiconductor wafer in a plasmatreatment apparatus by setting the wafer on said wafer stage, whereinthe temperature of the refrigerant to be allowed to flow along therefrigerant flow paths is controlled on the basis of the temperature ofsaid substrate to be processed.
 10. A wafer stage comprising: a basematerial equipped with refrigerant flow paths for allowing a refrigerantfor temperature adjustment to flow, a stress-reducing member brazed tothe wafer setting side of said base material and having a smallerthermal expansion coefficient than does said base material, a dielectricfilm provided on the wafer setting side of said stress-relaxing member,and a deflection-preventing member brazed to the wafer non-setting sideof said base material and having a smaller thermal expansion coefficientthan does said base material.